1. Field of the Invention
The present invention relates to a semiconductor memory cell, and more particularly to a semiconductor memory cell in which a potential representing data written at a cell is increased so as to lengthen a refresh time of the cell and to thereby improve its integration.
2. Description of the Prior Art
FIG. 1 shows the construction of a general DRAM cell including a MOS transistor 1 and a capacitor 2. The MOS transistor 1 either writes bit data applied from a bit line BL into the cell by charging the capacitor 2 or reads the data written in the cell by transferring the charge on the capacitor 2 so as to output it to the bit line BL, in accordance with a signal on a word line WL applied to its gate electrode. FIG. 2 shows an operation of the general DRAM cell. In a first cell 1, as a signal on the word line WL1 is applied to the gate electrode of an MOS transistor 11, the MOS transistor 11 writes bit data on the bit line BL into a capacitor 12 or reads the written bit data from the capacitor 12 so as to output it to the bit line BL. In a second cell 2, as a signal on a word line WL2 is applied to the gate electrode of a MOS transistor 21, the MOS transistor 21 writes data of a bit line /BL into a capacitor 22 or reads the data written at the capacitor 22 to output it to the bit line /BL. The data read from a plurality of cells are amplified and output by a sense amplifier 30.